1. Field of the Invention
The present invention relates generally to a non-volatile memory device and an associated fabrication method. Particularly, the invention relates to a non-volatile memory device that incorporates a series of memory cells having memory elements comprising a bi-stable layer with programmable electrical resistance sandwiched between two conductive layers. Additionally, the invention relates to a method for manufacturing the non-volatile memory device that incorporates a process for simultaneously conditioning the transition metal oxide layer of each memory cell in a series such that the transition metal oxide layers exhibit a bi-stable electrical resistance.
2. Description of the Related Art
Flash erasable programmable read only memory (FEPROM or flash memory) is used in semiconductor devices and provides for rapid block erase operations. Flash memory generally requires only the use of one transistor per memory cell versus the two transistors per memory cell required for conventional electrically erasable programmable read only memory (EEPROM). Thus, flash memory takes up less space on a semiconductor device and is less expensive to produce. However, the need to develop further space saving components and to remain cost efficient in the fabrication of semiconductor devices continues. To that end, the use of materials with programmable electrical resistance for semiconductor device applications has been studied. The electrical resistance of resistance-switching materials, including but not limited to transition metal oxide materials, can be changed significantly by external influences, including temperature, magnetic fields and electric fields. Electrical impulses applied to theses materials can “program” them, such that they exhibit a desired resistive property. Specifically, the following referenced articles, international application and U.S. Patent, all of which are hereby expressly incorporated by reference into the present invention for purposes including, but not limited to, indicating the background of the present invention and illustrating the state of the art, describe materials and classes of materials with programmable electrical resistance and simple electrical resistor devices made from these materials: “Reproducible switching effect in thin oxide films for memory applications” (A. Beck et al., Applied Physics Letters, Vol. 77, No. 1, Jul. 2000); “Current-driven insulator-conductor transition and non-volatile memory in chromium-doped SrTiO3 single crystals” (Y. Watanabe et al., Applied Physics Letters, Vol. 78, No. 23, Jun. 2001); “Electrical current distribution across a metal-insulator-metal structure during bi-stable switching” (C. Rossel et al., Journal of Applied Physics, Vol. 90, No. 6, Sep. 2001); U.S. Pat. No. 6,815,744 issued to Beck et al. on Nov. 9, 2004; and, U.S. Pat. No. 6,204,139 issued to Liu et al. on Mar. 20, 2001.
Transition metal oxide materials are one class of materials that can be conditioned such that they exhibit a bi-stable electrical resistance and, therefore, they have a wide range of potential applications. This conditioning process involves subjecting the insulating dielectric material to an appropriate electrical signal for a sufficient period of time in order to generate a confined conductive region in the transition metal oxide that can be reversibly switched between two or more resistance states. However, there is a large variation in the time required for conditioning transition metal oxides. Due to this large time variation, bulk conditioning of multiple memory elements is difficult because once a single memory element is conditioned, current must be limited in order to prevent the conditioned element from burning-out when subjected to additional current as other memory elements continue to undergo conditioning. Consequently, individual conditioning of each memory cell is generally required. This time-consuming process of conditioning each memory cell individually and the large variations in conditioning nominally identical programmable resistors used in the memory cells and in devices formed with such memory cells severely hinders manufacturability and is impractical for production type arrays. Therefore, there is a need in the art for both a semiconductor structure and a method that allow for simultaneous conditioning of multiple parallel memory elements in devices with multiple memory cells.